DI Manfred Schlägl

Portrait of DI Manfred Schlägl

DI Manfred Schlägl

Science Park 4, 3rd floor, room 0317
manfred.schlaegl@jku.at
+43 732 2468 4565

Publications

Conferences

[1] Katharina Ruep, Manfred Schlägl, and Daniel Große. Late breaking results: Float fight – verifying floating-point behavior in RISC-V simulators. In Design, Automation and Test in Europe Conference (DATE), 2026. [ bib ]
[2] Manfred Schlägl, Andreas Hinterdorfer, and Daniel Große. A RISC-V CHERI VP: Enabling system-level evaluation of the capability-based CHERI architecture. In Asia and South Pacific Design Automation Conference (ASP-DAC), 2026. [ bib | sourcecode | .pdf ]
[3] Manfred Schlägl, Jonas Reichhardt, and Daniel Große. ProtoLens: dynamic transaction visualization in virtual prototypes. In Forum on Specification and Design Languages (FDL), pages 1–8, 2025. [ bib | DOI | sourcecode | .pdf ]
[4] Shahzad Ahmad, Stefan Rass, Maksim Goman, Manfred Schlägl, and Daniel Große. Control flow protection by cryptographic instruction chaining. In International Conference on Security and Cryptography (SECRYPT), pages 233–246, 2025. (Best Paper Candidate). [ bib | DOI | .pdf ]
[5] Manfred Schlägl and Daniel Große. FastISS RISC-V VP++: A simulation performance evaluation of RVV workloads. In RISC-V Summit Europe, 2025. [ bib | .pdf ]
[6] Manfred Schlägl and Daniel Große. Fast interpreter-based instruction set simulation for virtual prototypes. In Design, Automation and Test in Europe Conference (DATE), pages 1–7, 2025. [ bib | DOI | sourcecode | .pdf ]
[7] Manfred Schlägl and Daniel Große. Single instruction isolation for RISC-V vector test failures. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 156:1–156:9, 2024. [ bib | DOI | sourcecode | .pdf ]
[8] Manfred Schlägl and Daniel Große. Bounded load/stores in grammar-based code generation for testing the RISC-V vector extension. In RISC-V Summit Europe, 2024. [ bib | sourcecode | .pdf ]
[9] Manfred Schlägl, Moritz Stockinger, and Daniel Große. A RISC-V “V” VP: Unlocking vector processing for evaluation at the system level. In Design, Automation and Test in Europe Conference (DATE), pages 1–6, 2024. [ bib | DOI | sourcecode | .pdf ]
[10] Manfred Schlägl and Daniel Große. GUI-VP Kit: A RISC-V VP meets Linux graphics - enabling interactive graphical application development. In ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 599–605, 2023. [ bib | DOI | sourcecode | .pdf ]
[11] Lucas Klemmer, Manfred Schlägl, and Daniel Große. RVVRadar: a framework for supporting the programmer in vectorization for RISC-V. In ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 183–187, 2022. [ bib | DOI | sourcecode | .pdf ]

Workshops

[12] Manfred Schlägl and Daniel Große. RVVTS: A modular, open-source framework for positive and negative testing of the RISC-V “V” vector extension (RVV). In ITG/GI/GMM-Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen” (MBMV), 2025. [ bib | .pdf ]
[13] Manfred Schlägl, Christoph Hazott, and Daniel Große. RISC-V VP++: Next generation open-source virtual prototype. In Workshop on Open-Source Design Automation (OSDA), 2024. [ bib | sourcecode | .pdf ]

Others

[14] Manfred Schlägl, Christoph Hazott, and Daniel Große. Recent developments in open-source RISC-V virtual prototypes: From vector extensions, tracing to 3D-games. In Special Session at Forum on specification & Design Languages, 2023. [ bib | sourcecode ]